1. Field of the Invention
The present invention generally relates to technique on a semiconductor device, and more specifically, to the technique for applying a boosted voltage to a word line for a predetermined time in a static type semiconductor memory device.
2. Description of the Related Art
Recently, needs of portable appliances such as portable telephones are considerably increased, and thus a static type semiconductor memory device (to be referred to as an "SRAM" hereinafter) is widely utilized to store data required in such a portable appliance. This is because the portable appliance is generally operated by a battery built therein and the SRAM has such a merit that the data can be saved with low power consumption in a non-operating state of the portable appliance. Therefore, the SRAM is convenient for a long time operation. As a consequence, in order that the battery-operated portable appliance can be operated for longer time, it is strongly needed that the SRAM can be operated with a lower drive voltage and with a lower current consumption.
As a low power consumption type SRAM in which the need to reduce current consumption of such an SRAM in a standby mode is realized, there is known a full CMOS cell type SRAM which is composed of a P-channel transistor and an N-channel transistor, and a TFT (Thin-Film Transistor) cell type SRAM. However, in the full CMOS cell type SRAM, since the P-channel transistor and the N-channel transistors are both used, the chip size is increased. Also, in the TFT cell type SRAM, a polysilicon layer manufacturing step is further increased in an SRAM using a high resistance load type memory cell. Accordingly, the higher manufacturing cost is required in both the full CMOS cell type SRAM and the TFT cell type SRAM.
In an SRAM device having a memory capacity of approximately 1 Mbits, a high resistance load type cell is generally used. In addition, a resistance value of the high resistance polysilicon layer is increased such that data holding current flowing through the high resistance load type cell can be decreased as much as possible.
Also, for the need of lowering a drive voltage, read/write operations of the SRAM device are realized with a low voltage. In addition, a data holding mode is employed in a standby state to hold the written data in a voltage lower than the normal drive voltage (e.g., 2 V listed in catalog). As a result, the written data can be guaranteed. As a result, power consumption of the SRAM device in an non-operating state can be reduced.
The circuit structure of The above-described conventional SRAM device is described in, for example, Japanese Laid-open Patent Application (JP-A-Showa 63-282992) and Japanese Laid-open Patent Application (JP-A-Heisei 3-156795). The circuit structure of the SRAM device will now be described with reference to a circuit block diagram shown in FIG. 1A and a circuit structure of a memory section thereof shown in FIG. 1B.
That is, FIG. 1A shows a circuit structure of an SRAM device with employment of high resistance load type memory cells 10, in which (m.times.n) high resistance load type memory cells 10 are driven by "m" of word lines WL1, WL2, . . . made of polysilicon and by "n" digit (bit) line pairs DG1 and CDG1, DG2 and CDG2, . . . A word decoder 13 inputs address signals A0 to An, and a control signal 21 to select one of these word lines WL1, WL2, . . . Also, the control signal 21 is amplified by a buffer logic circuit 19 and the amplified control signal 21 is supplied to a dummy word line DWL1. A signal derived from this dummy word line DWL1 is supplied via a word line voltage boosting circuit 12 to the word decoder 13.
Each of the high resistance load type memory cells 10 is connected to a corresponding one of the word lines WL1, WL2, . . . Also, each of the high resistance load type memory cells 10 is connected to a corresponding pair of the bit line pairs DG1, CDG1: DG2, CDG2, . . . As shown in FIG. 1B, each of these high resistance load type memory cells 10 is composed of memory cell driving MOS transistor QD1 and QD2, transfer transistors QT1 and QT2 for the memory cell, and load resistors R.
FIGS. 2, 3A, 3B, 4A and 4B show waveform diagrams for explaining operations of the high resistance load type memory cell 10. That is, FIG. 2 shows an operation waveform diagram of the high resistance load type memory cell 10 when the operation state of this memory cell 10 is changed from the actual use state to the data holding state, and from the data holding mode to the actual use state. FIGS. 3A and 3B show internal operation waveform diagrams of the high resistance load type memory cell 10 in T seconds (i.e., time described in catalog and shown in FIG. 2) when the data read operation is carried out after the operation state of the memory cell 10 is changed from the data holding state to the actual use state. FIGS. 4A and 4B show operation waveform diagrams of data holding nodes "a" and "b" in the high resistance load type memory cell 10 when .alpha. ray is irradiated.
Referring now to FIG. 2, a description will be made of operations of the data holding nodes "a" and "b" of the high resistance load type memory cell 10 when the operation of this memory cell 10 is changed between the actual use state and the data holding state. Since the potential level of the word line is the ground level in the data holding state. When the voltage for the memory cell is changed between the voltage VCC in the actual use state and the voltage VDR in the data holding state, the potential at the high level side output node "a" is changed in accordance with the time constant, which is determined based on the resistance value of the high resistor element R and the load capacitance of the node "a".
It is now assumed that the operation of the memory cell 10 is changed from the data holding state to the actual use state. Also, it is assumed that the potential of the word line WL1 selected based on the address signals A0 to An is changed to the boosted word line voltage after the time T described in the catalog and then the read operation is carried out. In this case, the operation when the potential at the word line is not yet increased will now be described more in detail with reference to FIG. 3A and the operation when the potential at word line is still increased will now be described more in detail with reference to FIG. 3B.
As shown in FIG. 3A, in the case where the potential at the word line is not yet increased, the transfer transistor QT1 is not brought into the ON state, so that there is no change in the potential at the node "a". This is because the potential difference between the potential at the node "a" and the power supply voltage VCC in the actual use state is lower than the threshold voltage of the transfer transistor QT1. On the contrary, since the transfer transistor QT2 is brought into the ON state, the electric charges which have stored in the load of the bit line CDG1 will flow into the node "b". At this time, since the potential at the node "a" is low, the current ability of the drive MOS transistor QD2 using the potential at the node "a" as the gate potential is low. As a consequence, the potential at the node "b" is increased. Accordingly, the drive transistor QD1 is brought into the ON state so that there is no potential difference between the node "a" and the node "b". The potentials at the nodes "a" and "b" are inverted by a very small fluctuation in the current abilities of the drive transistors employed within the high resistance load type memory cell 10. As a result, the cell data would be destroyed.
However, as illustrated in FIG. 3B, in the case where the potential at the word line is boosted to the boosted voltage VBB higher than the threshold voltage of the transfer transistor QT1, both of the transfer transistors QT1 and QT2 are brought into the ON state. Accordingly, the electric charges will flow into the nodes "a" and "b" from the bit lines. As a result, the potential at the node "a" is increased. Even when the electric charge flows from the bit line into the node "b", the gate potential at the drive MOS transistor QD2 becomes high, so that the potential at the node "b" is not so increased. As a consequence, the data written into the high resistance load type memory cell 10 can be read without electrically destroying these written data.
In a 1-Mbit SRAM device having both of the above-described low current consumption operation mode and also a data holding mode, the low current consumption operation is realized by increasing the resistance value of the high resistance polysilicon layer in the high resistance load type memory cell 10. In this case, when the operation state of this memory cell 10 is changed from the data holding mode at the voltage of 2 V to the actual use state at the low operation voltage of 2.7 V, the long time period is required until a high level side output potential of this high resistance load type memory cell 10 is increased up to the power supply voltage in the actual use state. This is because the high level side output potential is applied via the high resistance load resistor. A high resistance load resistor element formed in a 1-Mbit SRAM device which is presently manufactured in mass production typically has the resistance value as high as 10 tera ohms, assuming that a consumed current in the standby state is selected to be on the order of 1 .mu.A.
On the other hand, the chip size of the SRAM device is still reduced every year. At the same time, the mask pattern of a high resistance load resistor of the memory cell is also reduced. Also, the resistance value of the high resistance load resistor determined based on a dose amount of phosphorus ions into a polysilicon layer is largely fluctuated in a range of 8 to 18 tera ohms.
Here, assume that a diffusion layer capacitance of a drain of a memory cell driving transistor for holding cell data is selected to be on the order of 1.3 fF and a gate capacitance of another memory cell driving transistor of a flip-flop is selected to be on the order of 1.3 fF. In this case, a potential rising time period required until the drain node reaches from a voltage in the data holding state up to a power supply voltage in the actual state would become (1.3.times.10.sup.-15 +1.3.times.10.sup.-15).times.(8 to 18 10.sup.12)=21 to 47 msec.
On the other hand, the wait time period described in the catalog is generally selected to be on the order of 5 msec. Therefore, the read operation would be carried out before the potential rising time period required when the high level side output potential of this high resistance load type memory cell 10 is increased to the power supply potential.
Now, the SRAM device is tried to be manufactured with lower cost, and as a result of this, the chip size of the SRAM device is reduced, as described above. Also, the cell size of the high resistance load type memory cell is reduced. Therefore, it becomes practically difficult to maintain a current ability ratio of a cell transfer transistor to a cell driver transistor, namely (the current ability of the cell driver transistor)/(the current ability of the cell transfer transistor). The larger this current ability ratio is increased, the better the current holding ability of the high resistance load type memory cell is increased. As a result, the potential difference between the high level side output potential of the high resistance load type memory cell and the low level side output potential thereof is lowered, so that the cell data would be destroyed.
As previously explained, the time period originally required to increase the potential of the word line is about 21 to 47 msec. If time period during which the potential of the word line is boosted becomes longer than this originally required time period, then the current ability of the cell transfer transistor is increased, so that the current ability ratio of this cell transfer transistor to the cell driver transistor is decreased. Therefore, there is another problem in that the .alpha.-ray endurance amount would be lowered.
Next, operations of this high resistance load type memory cell when the .alpha.-ray is irradiated will now be explained with reference to FIGS. 4A and 4B. That is, FIG. 4A illustrates operation of the memory cell 10 when the potential at the word line is not increased, whereas FIG. 4B shows operation of the memory cell 10 when the potential at the word line is increased, while the .alpha.-ray is irradiated. When the potential at the word line is increased, the gate voltages of the transfer transistors QT1 and QT2 are increased. Accordingly, the current abilities thereof are increased. However, when one word line is selected and the potential at this word line becomes the high level, the potential at the node "b" on the low level side of the cell data is increased in the case where the potential at the word line is increased as shown FIG. 4B than in the case where the potential at the word line is not increased as shown FIG. 4A. In this case, if the .alpha.-ray is irradiated at time to, the potential drop may easily occur in the node "a" at the high level potential when the potential at the node "b" is high. This is because the above-described current ability ratio of the transfer transistor QT1 to the driver transistor QD1 is lowered. Accordingly, the cell data would be readily destroyed.
As described above, the word line voltage is desirably boosted in the data read operation in the SRAM device. However, if the read/write operation of the SRAM device is waited until the high level side output potential reaches the power supply potential, there is another problem in that the operation of an overall system would be delayed. Also, if the word line voltage is boosted for too long time, the .alpha.-ray endurance would be lowered. Therefore, the word line voltage boosting operation should be stopped after a predetermined time period.
To avoid the problems, the conventional circuit shown in FIG. 1 is proposed to control the time period required to boost the potential at the word line. In this conventional time control circuit, the word line voltage boosting circuit 12 is driven using the dummy word line DWL1 until the boosted potential at the dummy word line DWL1 becomes the power supply voltage. Thus, the dummy word line DWL1 is employed so as to confirm that any one of the word lines is selected.
As previously described, the time period originally required to increase the potential at the word line is about 21 to 47 msec. However, in the conventional circuit in which the word line voltage boosting circuit 12 is driven using the dummy word line DWL1, it is practically difficult to produce such long delay time with high precision.
Also, it is difficult to realize such a long delay time by a delay circuit composed of inverters. In other words, even when this inverter type delay circuit is constituted under the worst condition, the normal operation speed of an SRAM device is selected to be on the order of "nsec" (nanosecond). On the other hand, when this inverter type delay circuit is constituted of inverters, a large number of inverter elements are necessarily required, because the operation speed on the order of "msec" (millisecond) is longer than "nsec" by 6 digits. As a consequence, the chip area is increased, and further the higher cost is required. Thus, it is practically impossible to construct such a long time delay circuit of inverters.
Further, it is extremely difficult to produce a timer circuit composed of a resistor R and a capacitor C such that the delay time is adjusted so as to be fitted to the high resistance value of the high resistance load type memory cell. This is because the high resistance value would be fluctuated by the manufacturing condition. That is, the resistance value of the high resistor element is largely changed by the manufacturing condition of polysilicon. In addition, the number of high resistance elements is 2 million in a 1-Mbit high resistance load type SRAM. Therefore, fluctuations in these resistance values are considerably increased.
An SRAM device is disclosed in, for instance, Japanese Laid-open Patent Application (JP-A-Heisei 5-6675), in which the word line voltage boosting circuit is used to realize the write operation with a low voltage. In this conventional example, the high level side output potential of a high resistance load type memory cell is applied from a bit line by a word line voltage boosting circuit in the write operation. As a result, a large potential differences is given between the high level side output potential of the high resistance load type memory cell and also to the low level side output potential thereof. However, the boosting operation is performed only to the write operation.